| A Coherent VLSI Design Environment. (2002) | |||||||||
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Abstract | |||||||||
| This report covers the period from April 1, 1985 through September 30, 1985. The research discussed here is described in more detail in several published and unpublished reports cited. The CAD frame Schema has progressed to the point where it is useful for ample chip designs. The interface to CIF is complete, and work has begun on importing layout libraries. An interface to EDIF is being installed. Simulators can now be connected, and thought is going into organization of VLSI libraries. A plan for the distribution of Schema is now being worked out. Members of the DARPA VLSI community will be able to get copies in the Fall of 1985 or Spring of 1986. Previous results on waveform bounding have been generalized to large classes of problems described in canonical control-theory form. Work has begun on models for interconnect taking account of line inductance. This domain is less general that RLC networks, and there is hope that some of the previously derived bounds still apply. Indeed, some such results are reported here. During this period a novel device, the UV write-enabled PROM, was reported at a conference. Work continues on developing useful circuits employing this device. | |||||||||
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