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Design Space Exploration and Optimization of Embedded Cache Systems via a Compiler (1998)

Abstract
Presentation on design space exploration and optimization of embedded cache systems via a compiler.. See also ADM001473. The original document contains color images. Presented at High Performance Embedded Computing (HPEC) Workshop (6th) held in Lexington, MA on 24-26 Sep 2002.

Publication details
Download http://handle.dtic.mil/100.2/ADA419871
Contributors GEORGIA INST OF TECH ATLANTA
Repository Defense Technical Information Center OAI-PMH Repository (United States)
Keywords COMPUTER PROGRAMMING AND SOFTWARE, *COMPILERS, DATA PROCESSING, OPTIMIZATION, SYSTEMS ENGINEERING, WORKSHOPS., BRIEFING CHARTS, CACHE SYSTEMS
Language eng